1. Field of the Invention
This invention is generally related to frequency synthesizers. More particularly, the invention relates to phase-locked loops that include loop filters integrated entirely on a semiconductor chip.
2. Related Art
Frequency synthesizers are regularly employed in communication transceivers used in numerous types of communication systems and communication technologies. The frequency synthesizer typically includes a phase-locked loop comprising an oscillator, such as a voltage-controlled oscillator, a loop filter, and a phase-frequency detector. A problem with conventional phase-locked loop designs is that the conventional loop filter consists of capacitors that often consume too much space to practically allow integration on a chip.
FIG. 1 is a block diagram that illustrates an example phase-locked loop (PLL) 160. The phase-locked loop 160 includes a phase-frequency detector (PFD) 162, a charge pump (CP) 164, a loop filter 166, a voltage-controlled oscillator (VCO) 168, and a divide-by-N (/N) module 170. Note that N can be a fractional or integer value. Although shown using a divide-by-N module 170, the phase-locked loop 160 can also be implemented using a mixer in place of the divide-by-N module 170. The use of a mixer in place of the divide-by-N module 170 provides an architecture that is known in the industry as an “offset-phase-locked loop” or “translational loop.” The phase-locked loop 160 locks the output signal of the VCO 168 to a clock signal (designated reference signal, Vref) that is N times lower in frequency than the VCO output signal.
The PFD 162 controls the frequency of the output signal of the VCO 168. The PFD 162 of the phase-locked loop 160 receives the divided VCO output signal from the divide-by-N module 170 at one input terminal and compares the phase and frequency of the divided VCO output signal to the reference signal, Vref, received at the other input terminal. Based on the comparison of the divided VCO output signal to the reference signal, the PFD 162 generates control signals to the charge pump 164, which generates a control signal (e.g., current signal) that is low-pass filtered by the loop filter 166 and then provided to the VCO 168. The filtered control signal output from the loop filter 166 is received by a varactor (not shown) in the VCO 168. The filtered control signal from the loop filter 166 tunes the varactor by changing the voltage across the varactor, thereby changing the frequency (and the phase) of the output signal of the VCO 168. The output signal of the VCO 168 is then divided down by the divide-by-N module 170 for comparison with the lower clock frequency, Vref, at the PFD 162 to adjust to the same phase and frequency.
The loop filter 166 generally comprises an integrating capacitor 174, with a value generally in the range of a few hundred pico-Farads for UHF (ultra-high-frequency) phase-locked loops. The integrating capacitor 174 is configured in parallel with a series R-C combination (i.e., a resistor 171-capacitor 173 series arrangement), which creates a low-frequency zero in the frequency response of the loop filter 166. A low-frequency zero can improve stability of the phase-locked loop 160. One well-known mechanism for creating a low-frequency zero is by using a large capacitor (e.g., capacitor 173 is typically in the range of a few nano-Farads). The integrating capacitor 174 is also in parallel with another R-C combination (resistor 172 and capacitor 175), which attenuates high-frequency signal components that are output from the charge pump 164 and creates a high-frequency pole in the frequency response of the loop filter 166. These resistor-capacitor networks of the loop filter 166 pose integration difficulties with the rest of the phase-locked loop components because of the large amount of space consumed to realize the needed capacitance (e.g., in the few nano-Farads range).
Several attempts at integrating a loop filter onto a chip are known in the art. One example implementation is illustrated in FIG. 2A. FIG. 2A is a block diagram of an example phase-locked loop (PLL) 260 configured with what is known in the art as a dual-path loop filter 266. This circuit is described in further detail in “A 1.5V 900 MHz Monolithic CMOS Fast-Switching Frequency Synthesizer For Wireless Applications,” by C. W. Lo, H. C. Luong, in the 2000 Symposium on VLSI Circuit Digest of Technical papers, pp. 238–241, herein incorporated by reference. The phase-locked loop 260 includes a phase-frequency detector (PFD) 262, a charge pump (CP) system 264 comprising charge pump modules 269a and 269b, a loop filter 266, a voltage-controlled oscillator (VCO) 268, and a divide-by-N (/N) module 270. The general principles of operation for the phase-locked loop 260 are similar to that described for the phase-locked loop 160 of FIG. 1. However, in the example phase-locked loop 260, the charge pump system 264 includes two modules 269a and 269b that provide current signals ICP1 and ICP2 on output connections 280 and 282, respectively. Connections 280 and 282 are a point of origination for dual paths of the loop filter 266. The current signals from each module 269a and 269b are a ratio of each other (e.g., they both increase or decrease based on the signals from the PFD 262). Generally, the current values at connections 280 and 282 are different (e.g., 10 microamperes versus 100 microamperes, respectively). The use of dual paths carrying current signals that are a ratio of each other provides a mechanism to obtain low-frequency zeroes for the frequency response of the loop filter 266 while enabling a reduction in the size of the capacitors of the loop filter 266 to conserve chip area.
The loop filter 266 comprises R-C networks configured as an integrator 284 in the path corresponding to connection 280, and a low-pass filter (LPF) 286 in the path corresponding to connection 282. Signals from the integrator 284 and the LPF 286 are provided on separate connections 290 and 291 to the VCO 268, which is shown in further detail in FIG. 2B.
The VCO 268 includes, among other components, back-to-back varactors 202 and 204. Varactor 202 includes back-to-back, reverse-biased diodes 206 and 208, and varactor 204 includes back-to-back, reverse-biased diodes 210 and 212. The output of the integrator 284 (FIG. 2A) is provided over connection 290 to node 218 corresponding to varactor 202. The output of the LPF 286 (FIG. 2A) is provided over connection 291 to node 220 corresponding to varactor 204. Diodes 206, 208, 210, and 212 are weighted to enable summation of the outputs of the integrator 284 and LPF 286 in the capacitance domain. Typically, one varactor set will have a KVCO (i.e., the control characteristic of a VCO in frequency per voltage) that is scaled in comparison to the other set. For example, varactor 202 may have a KVCO of approximately 10 mega-Hertz (MHz) per volt, whereas the other varactor 204 may be ten times less in KVCO value. Thus, the varactors 202 and 204 of the VCO 268 combine the different filtering characteristics of the loop filter paths, enabling smaller capacitance values for the loop filter 266 than those utilized in the loop filter 166 (FIG. 1) for the phase-locked loop 160 of FIG. 1. Yet, the output signal of the phase-locked loop 260 approximates the output signal provided in the phase-locked loop 160.
Similar dual-path solutions have been disclosed. In J. Craninckx and M. Steyaert's article, “A Fully-Integrated CMOS DCS-1800 Frequency Synthesizer,” IEEE Journal of Solid State Circuit (JSSC), December 1998, pp. 2054–2065, herein incorporated by reference, a dual-path loop filter is used to create a low-frequency zero in the frequency response of the loop filter by adding an integrator path and a low-pass filter path. Each of these paths has a separate charge pump modules, as shown in FIG. 2A. This implementation is disclosed using two active devices to do the summation of the two paths. However, the active components can create extra noise.
Another solution is described in the 2001 Symposium on VLSI Circuits Digest of Technical Papers, pp. 43-46, entitled, “A Fully-Integrated CMOS Frequency Synthesizer With Charge-Averaging Charge Pump And Dual-Loop Path Filter for PCS and Cellular CDMA Wireless Systems,” by Y. Yoo, et al., herein incorporated by reference. In this implementation, a unity gain buffer is used to combine the two paths, thus using only a single active device.
Although some of these implementations facilitate the integration on-chip of loop filters by reducing the capacitance and consequently the area consumed by the capacitive device, it would be desirable to provide a phase-locked loop having a loop filter integrated on chip and having reduced complexity and improved noise performance while not significantly altering the loop transfer characteristics.